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"Implications of VHDL timing models on simulation and software synthesis."
Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee (1997)
- Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
Implications of VHDL timing models on simulation and software synthesis. J. Syst. Archit. 44(1): 23-36 (1997)
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