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ORCID"VHDL generation from a timed extension of the formal description technique ..."
Carlos Delgado Kloos et al. (1993)
- Carlos Delgado Kloos, Tomás Pedro de Miguel Moro, Tomás Robles Valladares, Guadalberto Rabay Filho, Andrés Marín López:
VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project. Microprocess. Microprogramming 38(1-5): 589-596 (1993)
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