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"VLSI Design and Hardware Implementation of High-Speed Energy-Efficient ..."

Rahul Shrestha, Roy P. Paily (2015)

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DOI: 10.1166/JOLPE.2015.1391

access: closed

type: Journal Article

metadata version: 2020-10-26

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Rahul Shrestha, Roy P. Paily:
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. J. Low Power Electron. 11(3): 406-412 (2015)

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