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"Optimized Fault-Tolerant Adder Design Using Error Analysis."

Raghavendra Kumar Sakali et al. (2023)

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DOI: 10.1142/S0218126623500913

access: closed

type: Journal Article

metadata version: 2023-08-06

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  dblp key:
  - journals/jcsc/SakaliBRVM23
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  - https://dblp.org/rec/journals/jcsc/SakaliBRVM23
Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Optimized Fault-Tolerant Adder Design Using Error Analysis. J. Circuits Syst. Comput. 32(6): 2350091:1-2350091:32 (2023)

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