"High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid ..."

Avadhoot Khairnar et al. (2022)

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DOI: 10.1142/S0218126622502000

access: closed

type: Journal Article

metadata version: 2022-08-25

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Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi:
High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. J. Circuits Syst. Comput. 31(11): 2250200:1-2250200:16 (2022)

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