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"Unified Technique for on-Line Testing of Digital Circuits: Delay and ..."

Santosh Biswas et al. (2008)

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DOI: 10.1142/S0218126608004757

access: closed

type: Journal Article

metadata version: 2021-03-08

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  - https://dblp.org/rec/journals/jcsc/BiswasMPS08
Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar:
Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models. J. Circuits Syst. Comput. 17(6): 1069-1089 (2008)

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