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"Size Optimization Technique for Logic Circuits that Considers BTI and ..."

Michitarou Yabuuchi, Kazutoshi Kobayashi (2016)

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DOI: 10.2197/IPSJTSLDM.9.72

access: closed

type: Journal Article

metadata version: 2020-09-29

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Michitarou Yabuuchi, Kazutoshi Kobayashi:
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. IPSJ Trans. Syst. LSI Des. Methodol. 9: 72-78 (2016)

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