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"An integrated DFT solution for power reduction in scan test applications ..."

Mahshid Mojtabavi Naeini et al. (2017)

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DOI: 10.1016/J.VLSI.2016.12.009

access: closed

type: Journal Article

metadata version: 2020-02-20

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Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue:
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57: 108-124 (2017)

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