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"AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation."

Nuno Lourenço et al. (2016)

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DOI: 10.1016/J.VLSI.2016.04.009

access: closed

type: Journal Article

metadata version: 2020-02-20

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Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta:
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. 55: 316-329 (2016)

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