"Floorplan-aware analog IC sizing and optimization based on topological ..."

Nuno Lourenço et al. (2015)

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DOI: 10.1016/J.VLSI.2014.07.002

access: closed

type: Journal Article

metadata version: 2020-02-20

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Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta:
Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. 48: 183-197 (2015)

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