"Improved predictability, timing yield and power consumption using ..."

Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh (2011)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2010.10.001

access: closed

type: Journal Article

metadata version: 2020-02-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/JahanianZS11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/JahanianZS11
Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh:
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. Integr. 44(2): 123-135 (2011)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.