"Design of implicit pulsed-dual edge triggering flip flop for low power and ..."

P. Nagarajan, N. Ashok Kumar, P. Venkat Ramana (2020)

> Home

Details and statistics

DOI: 10.1142/S0219691319410091

access: closed

type: Journal Article

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ijwmip/NagarajanKR20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ijwmip/NagarajanKR20
P. Nagarajan, N. Ashok Kumar, P. Venkat Ramana:
Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems. Int. J. Wavelets Multiresolution Inf. Process. 18(1): 1941009:1-1941009:19 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.