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"Optimised fault tolerant core-based ASIC design for SRAM."

T. Suresh, Z. Brijet (2021)

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DOI: 10.1504/IJMTM.2021.121573

access: closed

type: Journal Article

metadata version: 2022-04-11

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T. Suresh, Z. Brijet:
Optimised fault tolerant core-based ASIC design for SRAM. Int. J. Manuf. Technol. Manag. 35(6): 485-493 (2021)

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