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ORCID"Test power reduction and test pattern generation for multiple faults using ..."
J. P. Anita, P. Sudheesh (2016)
- J. P. Anita
, P. Sudheesh:
Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams. Int. J. High Perform. Syst. Archit. 6(1): 51-60 (2016)
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