"Low-Latency Connected Component Labeling Using an FPGA."

Yasuaki Ito, Koji Nakano (2010)

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DOI: 10.1142/S0129054110007337

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type: Journal Article

metadata version: 2023-11-12

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Yasuaki Ito, Koji Nakano:
Low-Latency Connected Component Labeling Using an FPGA. Int. J. Found. Comput. Sci. 21(3): 405-425 (2010)

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