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"A low jitter and fast locking all digital phase locked loop with flash ..."

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal (2022)

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DOI: 10.1002/CTA.3292

access: closed

type: Journal Article

metadata version: 2022-09-10

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  - https://dblp.org/rec/journals/ijcta/SahaniSA22
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. Int. J. Circuit Theory Appl. 50(8): 2900-2912 (2022)

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