Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Power efficient low latency architecture for decoder: Breaking the ACS ..."

Subramanyam Radha, David Sundararaj Shylu, Perattur Nagabushanam (2019)

> Home

Details and statistics

DOI: 10.1002/CTA.2663

access: closed

type: Journal Article

metadata version: 2020-05-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ijcta/RadhaSN19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ijcta/RadhaSN19
Subramanyam Radha, David Sundararaj Shylu, Perattur Nagabushanam:
Power efficient low latency architecture for decoder: Breaking the ACS bottleneck. Int. J. Circuit Theory Appl. 47(9): 1513-1528 (2019)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.