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"Design of a parity preserving reversible full adder/subtractor circuit."

Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast (2018)

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DOI: 10.1504/IJCISTUDIES.2018.10011247

access: closed

type: Journal Article

metadata version: 2020-04-01

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  - journals/ijcistudies/ArabaniRH18
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  - https://dblp.org/rec/journals/ijcistudies/ArabaniRH18
Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast:
Design of a parity preserving reversible full adder/subtractor circuit. Int. J. Comput. Intell. Stud. 7(1): 19-32 (2018)

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