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ORCID"Power gating architecture implementation inside clock period to reduce power."
Debanjali Nath et al. (2014)
- Debanjali Nath, Priyanka Choudhury
, Abhishek Nag, Sambhu Nath Pradhan:
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6(3): 310-323 (2014)
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