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"A Systematic Methodology for Design and Worst-Case Error Analysis of ..."

Takahiro Yamamoto et al. (2017)

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DOI: 10.1587/TRANSFUN.E100.A.1496

access: closed

type: Journal Article

metadata version: 2020-10-26

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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/YamamotoTTYH17
Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1496-1499 (2017)

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