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"A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR ..."

Hidehiro Toyoda et al. (2007)

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DOI: 10.1093/IETELE/E90-C.10.1957

access: closed

type: Journal Article

metadata version: 2020-04-11

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Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada:
A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications. IEICE Trans. Electron. 90-C(10): 1957-1963 (2007)

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