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"Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit."

Koichi Tanno et al. (2005)

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DOI: 10.1093/IETFEC/E88-A.10.2696

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/TannoSTI05
Koichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka:
Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(10): 2696-2698 (2005)

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