"A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed ..."

Vahid Majidzadeh, Omid Shoaei (2006)

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DOI: 10.1093/IETELE/E89-C.6.692

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type: Journal Article

metadata version: 2020-04-11

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Vahid Majidzadeh, Omid Shoaei:
A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications. IEICE Trans. Electron. 89-C(6): 692-701 (2006)

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