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"Chip-Level Substrate Coupling Analysis with Reference Structures for ..."

Daisuke Kosaka et al. (2007)

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DOI: 10.1093/IETFEC/E90-A.12.2651

access: closed

type: Journal Article

metadata version: 2020-04-11

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Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2651-2660 (2007)

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