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ORCID"Design for Delay Fault Testability of Dual Circuits Using Master and Slave ..."
Kentaroh Katoh, Kazuteru Namba, Hideo Ito (2009)
- Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. 92-D(3): 433-442 (2009)
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