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"Analytical Stability Modeling for CMOS Latches in Low Voltage Operation."

Tatsuya Kamakari et al. (2016)

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DOI: 10.1587/TRANSFUN.E99.A.2463

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - journals/ieicet/KamakariSIO16
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/KamakariSIO16
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2463-2472 (2016)

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