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"A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free ..."

Shinya Kajiyama et al. (2009)

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DOI: 10.1587/TRANSELE.E92.C.1258

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/KajiyamaFKMYS09
Shinya Kajiyama, Masamichi Fujito, Hideo Kasai, Makoto Mizuno, Takanori Yamaguchi, Yutaka Shinagawa:
A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers. IEICE Trans. Electron. 92-C(10): 1258-1264 (2009)

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