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"Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for ..."

Koichiro Ishibashi et al. (2006)

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DOI: 10.1093/IETELE/E89-C.3.250

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/IshibashiFYOAHSMITIKHT06
Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 250-262 (2006)

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