Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at ..."

Yoshinobu Higami et al. (2008)

> Home

Details and statistics

DOI: 10.1093/IETISY/E91-D.3.690

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/HigamiSTKT08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/HigamiSTKT08
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. 91-D(3): 690-699 (2008)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.