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"A low-voltage CMOS MIN circuit with 3N+1 complexity and 10mV/10ns ..."

Jesús Ezequiel Molinar-Solís et al. (2013)

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DOI: 10.1587/ELEX.10.20130755

access: open

type: Journal Article

metadata version: 2021-07-25

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  - journals/ieiceee/Molinar-SolisMGHSRDS13
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  - https://dblp.org/rec/journals/ieiceee/Molinar-SolisMGHSRDS13
Jesús Ezequiel Molinar-Solís, Carlos Muñiz-Montero, Rodolfo Zolá García-Lozano, Cuauhtémoc Hidalgo-Cortés, Luis Abraham Sánchez-Gaspariano, José Miguel Rocha-Pérez, Alejandro Díaz-Sánchez, Jesús Efraín Gaxiola Sosa:
A low-voltage CMOS MIN circuit with 3N+1 complexity and 10mV/10ns corner error. IEICE Electron. Express 10(22): 20130755 (2013)

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