"Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity."

Kenji Kogo et al. (2017)

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DOI: 10.1587/ELEX.14.20171017

access: open

type: Journal Article

metadata version: 2021-02-12

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  - https://dblp.org/rec/journals/ieiceee/KogoNKK17
Kenji Kogo, Takayasu Norimatsu, Norihiro Kohmu, Takashi Kawamoto:
Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity. IEICE Electron. Express 14(23): 20171017 (2017)

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