"Design of hierarchical cache coherence protocol based on Chiplet architecture."

Jianghua Gui et al. (2025)

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DOI: 10.1587/ELEX.22.20250219

access: open

type: Journal Article

metadata version: 2025-08-28

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  - https://dblp.org/rec/journals/ieiceee/GuiLGLZ25
Jianghua Gui, Bing Li, Tongtong Guo, Anzhou Lai, Shuaishuai Zhang:
Design of hierarchical cache coherence protocol based on Chiplet architecture. IEICE Electron. Express 22(12): 20250219 (2025)

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