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"A 12.5 Gbps clock and data recovery circuit with phase interpolation based ..."
Gang Chen, Min Gong, Chun Deng (2020)
- Gang Chen, Min Gong, Chun Deng:
A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop. IEICE Electron. Express 17(20): 20200302 (2020)
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