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"Verisym: Verifying Circuits by Symbolic Simulation."

William Adams, Warren A. Hunt Jr., Damir Jamsek (2003)

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DOI: 10.1023/A:1022977607142

access: closed

type: Journal Article

metadata version: 2020-03-13

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  - https://dblp.org/rec/journals/fmsd/AdamsHJ03
William Adams, Warren A. Hunt Jr., Damir Jamsek:
Verisym: Verifying Circuits by Symbolic Simulation. Formal Methods Syst. Des. 22(2): 163-173 (2003)

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