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"A process-tolerant low-power adder architecture for image processing ..."

Bharat Garg, G. K. Sharma (2019)

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DOI: 10.3906/ELK-1809-8

access: open

type: Journal Article

metadata version: 2021-06-04

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  dblp key:
  - journals/elektrik/GargS19
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  - https://dblp.org/rec/journals/elektrik/GargS19
Bharat Garg, G. K. Sharma:
A process-tolerant low-power adder architecture for image processing applications. Turkish J. Electr. Eng. Comput. Sci. 27(3): 1839-1854 (2019)

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