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"Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC ..."

Kokila Jagadeesh et al. (2019)

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DOI: 10.3311/PPEE.13424

access: open

type: Journal Article

metadata version: 2023-05-24

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  - https://dblp.org/rec/journals/eecs/JagadeeshDBR19
Kokila Jagadeesh, Arjun Murali Das, B. Shameedha Begum, Natarajan Ramasubramanian:
Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture. Period. Polytech. Electr. Eng. Comput. Sci. 63(4): 244-253 (2019)

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