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"Design of Reversible Arithmetic Logic Unit with Built-In Testability."

Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar (2019)

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DOI: 10.1109/MDAT.2019.2919017

access: closed

type: Journal Article

metadata version: 2022-07-14

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  - journals/dt/GaurSG19
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  - https://dblp.org/rec/journals/dt/GaurSG19
Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar:
Design of Reversible Arithmetic Logic Unit with Built-In Testability. IEEE Des. Test 36(5): 54-61 (2019)

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