"Understanding Yield Losses in Logic Circuits."

Davide Appello et al. (2004)

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DOI: 10.1109/MDT.2004.21

access: closed

type: Journal Article

metadata version: 2022-10-02

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  - https://dblp.org/rec/journals/dt/AppelloFGTGM04
Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew:
Understanding Yield Losses in Logic Circuits. IEEE Des. Test Comput. 21(3): 208-215 (2004)

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