"Design of a novel low-latency parameterizable posit adder/subtractor using ..."

Bahadir Özkilbaç, Tevhit Karacali (2024)

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DOI: 10.1016/J.DSP.2024.104718

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type: Journal Article

metadata version: 2024-09-08

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Bahadir Özkilbaç, Tevhit Karacali:
Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA. Digit. Signal Process. 155: 104718 (2024)

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