"Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing ..."

Haroon S. Rasheed, Rajeev Pankaj Nelapati (2025)

> Home

Details and statistics

DOI: 10.1007/S00034-024-02935-4

access: closed

type: Journal Article

metadata version: 2025-05-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/RasheedN25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/RasheedN25
Haroon S. Rasheed, Rajeev Pankaj Nelapati:
Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay. Circuits Syst. Signal Process. 44(4): 2242-2265 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.