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"A Low Error, Hardware Efficient Logarithmic Multiplier."

L. Guna Sekhar Sai Harsha et al. (2022)

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DOI: 10.1007/S00034-021-01793-8

access: closed

type: Journal Article

metadata version: 2023-06-26

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  - journals/cssp/HarshaJBVS22
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  - https://dblp.org/rec/journals/cssp/HarshaJBVS22
L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.:
A Low Error, Hardware Efficient Logarithmic Multiplier. Circuits Syst. Signal Process. 41(1): 485-513 (2022)

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