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ORCID"Benchmarking Large Language Models for Automated Verilog RTL Code Generation."
Shailja Thakur et al. (2022)
- Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri
, Brendan Dolan-Gavitt, Siddharth Garg:
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. CoRR abs/2212.11140 (2022)
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last updated on 2023-11-12 02:17 CET by the dblp team
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