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"FPGA and ASIC implementations of the etaT pairing in ..."

Jean-Luc Beuchat et al. (2010)

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DOI: 10.1016/J.COMPELECENG.2009.05.001

access: closed

type: Journal Article

metadata version: 2020-10-26

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  - journals/cee/BeuchatDFIIKKMOOSSSTVY10
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  - https://dblp.org/rec/journals/cee/BeuchatDFIIKKMOOSSSTVY10
Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto:
FPGA and ASIC implementations of the eta_T pairing in characteristic three. Comput. Electr. Eng. 36(1): 73-87 (2010)

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