"Low-Power FPGA Implementation of Convolution Neural Network Accelerator ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Chuanglu Chen et al. (2020)

> Home

- view
  - electronic edition via DOI (open access)
- export record
  dblp key:
  - journals/algorithms/ChenLZZHZ20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/algorithms/ChenLZZHZ20
Chuanglu Chen, Zhiqiang Li, Yitao Zhang, Shaolong Zhang, Jiena Hou, Haiying Zhang:
Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms 13(9): 213 (2020)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.