"Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning."

Pai-Yu Chen, Ligang Gao, Shimeng Yu (2016)

> Home

Details and statistics

DOI: 10.1109/TMSCS.2016.2598742

access: closed

type: Journal Article

metadata version: 2023-03-21

- view
  authority control:
- export record
  dblp key:
  - journals/tmscs/ChenGY16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tmscs/ChenGY16
Pai-Yu Chen, Ligang Gao, Shimeng Yu:
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. IEEE Trans. Multi Scale Comput. Syst. 2(4): 257-264 (2016)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.