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"A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders."

Hsie-Chia Chang et al. (2009)

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DOI: 10.1109/TCSI.2008.2010143

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/tcas/ChangLCL09
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1960-1967 (2009)

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