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"Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on ..."

Shouyi Yin et al. (2016)

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DOI: 10.1109/TCAD.2015.2512900

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/YinGLLW16
Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei:
Joint Modulo Scheduling and V_dd Assignment for Loop Mapping on Dual- V_dd CGRAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1475-1488 (2016)

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