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"POSET timing and its application to the synthesis and verification of ..."

Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng (1999)

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DOI: 10.1109/43.766727

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/MyersRM99
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  - https://dblp.org/rec/journals/tcad/MyersRM99
Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng:
POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 769-786 (1999)

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