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"Energy-efficient High-level Synthesis for HDR Architecture with ..."

Hiroyuki Akasaka et al. (2014)

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DOI: 10.2197/IPSJTSLDM.7.74

access: closed

type: Journal Article

metadata version: 2020-10-26

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Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 74-80 (2014)

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