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"Selecting test methodologies for PLAs and random logic modules in VLSI ..."

Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri (1989)

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DOI: 10.1016/0167-9260(89)90005-9

access: closed

type: Journal Article

metadata version: 2020-02-20

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Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri:
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach. Integr. 7(3): 267-281 (1989)

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